As feature sizes continue to scale down in semiconductor industry, the fabrication process of integrated circuit devices becomes more and more complex. Advanced semiconductor designs typically incorporate multilayer structures. For example, during the process of formation of a metal interconnect, usually a hardmask layer, a planarization layer and an antireflective coating (ARC) layer are sequentially formed on a substrate with a dielectric layer thereon. A photoresist layer is then formed on top of the ARC layer. The definition of the pattern is formed by photolithography on the photoresist layer. The resist pattern is transferred to the ARC layer via an etch process using the photoresist film as a mask. Similarly, the ARC pattern is transferred sequentially through all other underlying layers, and finally, a pattern is formed on the substrate.
During the deposition or the processing of the multilayer structures, if defects or other types of errors are found in any layer of the structures, the substrate must be reworked to prevent permanent damage to the entire batch of chips in subsequent processing. In addition, selective removing the multilayer structures is often necessary for purposes of performing defect yield analysis, and/or for electrical characterization or physical failure analysis of wafers, wafer fragments, individual dies, or packaged dies to perform reliability defect root cause analysis.
Reworking multilayer structures including low-k dielectric materials is problematic using known layer removal techniques such as conventional chemical-mechanical polish (CMP), or plasma or reactive ion etch processes. The fragile nature of the low-k dielectric materials causes them to react poorly to processes effective for oxide dielectrics. In addition, conventional layer removal processes used to remove overlying layers can result in damages to the underlying low-k dielectric layers.
New and improved processes are thus desirable which can selectively rework overlying layers without damaging the underlying low-k dielectric layers on a multilayer semiconductor substrate.